[https://nvbugs/6655990][test] Gate WAN multi-GPU LPIPS against a within-build reference and unwaive - #18386
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Included review availability: Your plan provides up to 12 included reviews per hour; 11 remain after this review. WalkthroughThe VisualGen multi-GPU and tensor-parallel LPIPS tests now use a session-scoped single-GPU reference. Each variant has a specific within-build threshold, and the frozen golden remains a quality backstop. The related skip waivers were removed. ChangesVisualGen LPIPS validation
Priority: ⬇️ Low Estimated code review effort: 3 (Moderate) | ~20 minutes Merge Risk: 🟡 Moderate · up to WAN multi-GPU tests may generate an expensive single-GPU reference even when the selected configuration lacks sufficient GPUs and would otherwise skip, consuming unnecessary CI capacity and potentially destabilizing test execution. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 18.18% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 11 functions across 2 files. (1 skipped: 1 unsupported.) ✨ Finishing Touches🧪 Generate unit tests (beta)
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…hin-build reference and unwaive The multi-GPU/TP WAN2.2 LPIPS tests exist to protect one invariant: parallelism does not change the output. They previously measured distance to a frozen golden video, which conflates parallelism error with whole-build numerics drift: PR NVIDIA#17693 (cuBLASLt GELU-tanh epilogue on the unquantized bf16 MLP path) applies GELU to the fp32 accumulator, shifting the bf16 rounding trajectory of every WAN2.2 run, and stepped [attn2d_2x2] 0.224261 -> 0.279512 across the 0.25 gate at post-merge build 2924 with no quality change. On an otherwise identical stack (4xB200, rc24 image, CI torch 2.12.0a0+...nv26.05), toggling only the NVIDIA#17693 mlp.py hunks moves two single-GPU fully-eager runs 0.2588 apart: the benign trajectory shift alone exceeds the old threshold, so golden-anchored gating cannot hold a tight bound. Restructure the gate (test names kept; test-db lists and waives.txt reference them): - Primary: score every variant against a fully-eager single-GPU reference generated in-session at the current build (session-scoped fixture; one ~3-minute generation amortized over all variants in the pytest session). Both sides shift together under benign numerics changes, so this gate fails only when parallelism itself changes the output. Calibrated per variant on 4xB200 across all ten variants on both the pre- and post-NVIDIA#17693 stacks; the distribution is bimodal: * exact class (0.05): ulysses4, cfg2_ulysses2 and cfg2_ulysses2_attn2d_2x1 reproduce the single-GPU output bit-exactly (LPIPS 0.000000) -- CFG splitting, Ulysses head repartition and the attn2d head-dim split are reduction-order invariant. The old 0.25 gate could not see even a total loss of that exactness; 0.05 can. * reduction-reordering class (0.32): TP GEMM splits and the attn2d sequence-KV split reorder floating-point reductions; the one-ULP seed amplifies over the 4 denoising steps to a saturation band (measured: tp2-family 0.2098/0.2036 on the post-/pre-NVIDIA#17693 stacks, attn2d_2x2-family 0.2597/0.2232, tp3 0.2618); compositions are bit-stable (cfg, ulysses and attn2d-head add exactly 0.0 on top of tp2 or attn2d_2x2). A genuinely different output (seed-43 control) measures 0.6656, well above the bound. - Backstop: keep the frozen-golden comparison at 0.32 as a catastrophic-quality bound. The single-GPU fully-eager run (the golden's own configuration) already measures 0.2223 (post-NVIDIA#17693) / 0.2568 (pre-NVIDIA#17693) against the golden, so distances inside the decorrelation band carry no signal; only far-from-everything outputs should fail it. - Remove the nvbug 6655990 waiver for [attn2d_2x2]. - _assert_lpips_below_threshold gains an optional label so a failing gate identifies itself in the junit message. Same root cause as nvbug 6655986 (LTX-2, recalibrated in PR NVIDIA#18384); this change additionally makes the WAN multi-GPU suite structurally immune to the drift class: within-build scores re-anchor at every build instead of accumulating against an aging golden. Signed-off-by: Chang Liu <9713593+chang-l@users.noreply.github.com>
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In `@tests/integration/defs/examples/visual_gen/test_visual_gen_multi_gpu.py`:
- Line 405: Change the wan22_within_build_reference session fixture usage to a
lazy, cached reference factory so reference generation is deferred until after
_skip_if_insufficient_gpus_for_parallel in _run_wan22_t2v_lpips_case. Invoke the
factory only after the GPU-capacity check, and apply the same adjustment to the
usage near the second multi-GPU test.
- Around line 239-267: Annotate every modified function with precise parameter
and return types, using existing concrete types and parallel-configuration
definitions rather than Any: update _wan22_reference_media_worker and
wan22_within_build_reference in
tests/integration/defs/examples/visual_gen/test_visual_gen_multi_gpu.py lines
239-267; _run_wan22_t2v_lpips_case at lines 334-336;
test_wan22_t2v_lpips_against_golden_multi_gpu at lines 399-406;
test_wan22_t2v_lpips_against_golden_tp at lines 420-427; and
_assert_lpips_below_threshold in
tests/integration/defs/examples/visual_gen/visual_gen_test_utils.py lines
628-630. Ensure fixture values, worker arguments, parallel configuration data,
and return values are all explicitly typed without changing behavior.
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Status update: direct push to the chang-l fork head is blocked by GitHub permissions, so the complete signed review fix is available as mergeable companion PR chang-l#6. It adds precise concrete types and defers the cached reference generation until after the GPU-capacity skip; complete file-scoped pre-commit passes. CI build 57342 failed in an unrelated DeepSeekV3Lite accuracy timeout, not in the WAN VisualGen paths. @chang-l please merge companion #6; once the original head updates, the two threads can be resolved and /bot run should be rerun. |
Signed-off-by: Chang Liu <9713593+chang-l@users.noreply.github.com>
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… under the within-build gate Bug 6535765's multi-GPU rows failed at build 2869 because PR NVIDIA#15762 (fused WAN2.2 AdaLN) shifted the whole-build bf16 trajectory: the single-GPU golden test failed 0.2393 (gate 0.05) in the same build, and [ulysses4]/[cfg2_ulysses2] inherited exactly that drift through the frozen-golden comparison. It was never a parallelism defect: on a post-NVIDIA#15762 stack both variants reproduce the same-build single-GPU output bit-exactly (within-build LPIPS 0.000000, calibration matrix in nvbug 6655990), and their frozen-golden score (0.2223) sits well inside the 0.32 backstop. Under the within-build gate these variants now assert the invariant the old comparison could not isolate -- parallelism does not change the output -- at the exact-class 0.05 bound, so remove the two multi-GPU waiver rows. The single-GPU row (test_visual_gen_wan.py::test_wan22_t2v_lpips_against_golden, 0.05 vs frozen golden) stays waived: it tracks the genuine NVIDIA#15762 numerics question (fix in flight: PR NVIDIA#17987) and is not covered by this gate. Signed-off-by: Chang Liu <9713593+chang-l@users.noreply.github.com>
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/bot run --extra-stage "DGX_B200-4_GPUs-PyTorch-Post-Merge-1, DGX_B200-4_GPUs-PyTorch-Post-Merge-2, DGX_B200-4_GPUs-PyTorch-Post-Merge-3, DGX_B200-4_GPUs-PyTorch-Post-Merge-4" |
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The within-build reference approach makes sense and directly tests the parallelism invariant. LGTM overall.
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…lpips-threshold-6655990 Signed-off-by: Chang Liu <9713593+chang-l@users.noreply.github.com> # Conflicts: # tests/integration/test_lists/waives.txt
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…lpips-threshold-6655990 Signed-off-by: Chang Liu <9713593+chang-l@users.noreply.github.com> # Conflicts: # tests/integration/test_lists/waives.txt
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Description
Closes nvbug 6655990 (post-merge WAN 2.2 multi-GPU LPIPS regression on B200, builds ≥ 2924).
Root cause. PR #17693 routes the unquantized bf16 MLP up-projection through a cuBLASLt GELU-tanh epilogue (
torch._addmm_activation(use_gelu=True)) that applies GELU to the fp32 accumulator instead of the bf16-rounded GEMM output. The per-layer delta is one bf16 ULP, but it shifts the bf16 rounding trajectory of every WAN2.2 run:test_wan22_t2v_lpips_against_golden_multi_gpu[attn2d_2x2]stepped 0.224261 → 0.279512 across the 0.25 gate exactly at post-merge build 2924 (deterministic across builds/nodes), with no quality change. Causally verified on 4×B200 (release:1.3.0rc24, same torch2.12.0a0+5aff3928d8.nv26.05as CI) by toggling only the #17693mlp.pyhunks — and, most tellingly: two single-GPU fully-eager runs differing only by those hunks measure LPIPS 0.2588 apart. The benign trajectory shift alone exceeds the old threshold, so a frozen-golden anchor cannot hold a tight bound (the golden's own configuration, single-GPU fully-eager, measures 0.2223/0.2568 against the golden on the post-/pre-#17693 stacks).Fix: gate the actual invariant. These tests exist to protect "parallelism does not change the output", so the primary gate now compares every variant against a fully-eager single-GPU reference generated in-session at the current build (session-scoped fixture, one ~3-minute generation amortized over all variants in the pytest session). Both sides shift together under benign whole-build numerics changes, so the #17693 class of breakage cannot fire this gate. The frozen golden is kept only as a loose catastrophic backstop (0.32), and the nvbug 6655990 waiver is removed.
Calibration (4×B200, all ten variants, measured on both the pre- and post-#17693 stacks). The within-build distribution is bimodal, so each variant carries its class threshold:
Findings baked into the class comments:
Test Coverage
test_wan22_t2v_lpips_against_golden_multi_gpu/..._tpvariants (names unchanged — test-db lists and the nvbug 6535765 waivers reference them) now assert the within-build gate plus the golden backstop; each_run_lpips_evalline and each assertion is labeled so failures identify the gate.[tp3]is declared inWAN22_LPIPS_TP_VARIANTSbut listed in no test-db file, so it does not run (thanks @yanxinzhangcs for catching it) — deliberately left for a follow-up so this PR's diff stays out oftests/integration/test_lists/test-db/, which pulls in three extra CODEOWNERS teams for a one-line test-list add.tp2covers the same TP-reordering class.[cfg2_ulysses2_attn2d_2x1]and[attn2d_2x2_ulysses2]sit in thesystem_gpu_count 8-8post-merge block, for whichjenkins/L0_Test.groovydefines noDGX_B200-8_GPUs-PyTorch-Post-Merge-*stage — that whole block is unreachable today. Both gaps are pre-existing and belong in a separate CI-infra change.[attn2d_2x2](nvbug 6655990) plus[cfg2_ulysses2]and[ulysses4](nvbug 6535765) unwaived here; exercised via--extra-stage "DGX_B200-4_GPUs-PyTorch-Post-Merge-1..4". All four passed the within-build gate on L0 build 58643.[tp2]+[attn2d_2x2]in one session (reference fixture generated once and reused, both gates evaluated) on the rc24+[TRTLLM-15398][perf] VisualGen MLP: cublasLt GELU-tanh epilogue for the unquantized bf16 path #17693 stack._assert_lpips_below_thresholdkeeps full backward compatibility (newlabelarg defaults to "").PR Checklist
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Dev Engineer Review
0.32as a catastrophic-quality backstop.nvbug 6655990waiver for the affected multi-GPU variants._assert_lpips_below_thresholdbackward compatibility.QA Engineer Review
test_wan22_t2v_lpips_against_golden_multi_gpu.test_wan22_t2v_lpips_against_golden_tp.wan22_within_build_referencefixture.tests/integration/test_lists/test-db/l0_dgx_b200.yml.attn2d_2x2,cfg2_ulysses2, andulysses4waivers fromtests/integration/test_lists/waives.txt.Update (2026-09-04): also unwaive the nvbug 6535765 multi-GPU rows
[ulysses4]and[cfg2_ulysses2](waived under nvbug 6535765) failed at build 2869 because PR #15762 (fused WAN2.2 AdaLN) shifted the whole-build trajectory — the single-GPU golden test failed 0.2393 (gate 0.05) in the same build, and the multi-GPU variants inherited that drift through the frozen-golden comparison. It was never a parallelism defect: on a post-#15762 stack both variants reproduce the same-build single-GPU output bit-exactly (within-build LPIPS 0.000000, calibration table above) and score 0.2223 against the frozen golden, inside the backstop. Under the within-build gate they now assert the correct invariant at the exact-class 0.05 bound, so this PR removes those two waiver rows as well.The single-GPU 6535765 row (
test_visual_gen_wan.py::test_wan22_t2v_lpips_against_golden, 0.05 vs frozen golden) intentionally stays waived — it tracks the genuine #15762 numerics question (fix in flight: PR #17987) and is outside this gate's scope.CI: retriggered with
--extra-stage "DGX_B200-4_GPUs-PyTorch-Post-Merge-1..4"so the newly unwaived variants execute regardless of chunk assignment.