fix(fpga_diff): support V3 partitions and ports

[klin02]

Summary

• Detect Kunminghu V2 from the generated SimTop io_riscv_halt_0 port.
• Define CPU_XIANGSHAN_KMHV2 for both Vivado and UVHS file lists.
• Guard the V2-only named halt-port connection in SimTop_wrapper.
• Keep the complete V2 core_with_l2 hierarchy on F2.
• Assign only V3 l2top to F1 while the V3 core and DiffTest host remain on F2.

Compatibility

Kunminghu V2 exports io_riscv_halt_0. Kunminghu V3 replaces it with io_riscv_wfi_0. The UVHS file list is regenerated before backend partitioning, so the same detected version selects both wrapper and partition behavior.

Verification

• Generated file lists from existing V2 and V3 FPGA releases.
• V2 emitted CPU_XIANGSHAN_KMHV2; V3 did not.
• Mocked UVHS partitioning: V2 created F0/F2 with route F2-F0; V3 created F0/F1/F2 with route F2-F0-F1.
• bash -n and Tcl completeness checks.

[klin02]

Lineage and extra changes:

• V2 source PR: none. The compatibility behavior was verified directly against kunminghu-v2 and kunminghu-v3 generated interfaces.
• V2 has io_riscv_halt_0; V3 has io_riscv_wfi_0 instead.
• Extra env-scripts work: generate CPU_XIANGSHAN_KMHV2 from the actual SimTop port, use it for the wrapper guard, and select whole-L2 V2 versus split-L2 V3 partitioning from the same generated file list.