Add FastH3 V2 MLX first-frame conditioning adapter

[atomantic]

Implement the FastH3 V2 MLX first-frame conditioning adapter in the pinned runner. Preserve the eight-step ladder, scheduler shifts, VSA, quantization cache identity, synchronized audio, and text-only behavior. Add synthetic tests for preprocessing, mask placement, invalid images, and schedule/audio invariants. Apple Silicon hardware is required for final render comparison. Part of #7805. When this ships, check its box in #7805 and close the epic if it is the last child.

[atomantic]

Needs upstream/runtime decision before safe implementation: the pinned FastVideo MLX entry script exposes text-only generate() arguments, and its pipeline denoise path has no image latent, first-frame mask, or conditioning-row API. A PortOS-only adapter would either silently discard the image or require reimplementing the upstream MLX algorithm. The final acceptance comparison also requires Apple Silicon hardware. Please provide or pin the intended upstream conditioning API/checkpoint contract before implementation.

[atomantic]

Model search (2026-09-22): no MLX checkpoint can take this adapter

Checked the published FastH3 V2 and MiniMax H3 MLX options against the pinned mlx_fasth3.py / MiniMaxH3MLXPipeline.generate contract. None of them is a first-frame API for this student.

• The V2 weights themselves do fl2va, but only in ComfyUI: MiniMaxH3ImageToVideo on FastVideo/FastVideo-FastH3-Comfy (fastvideo_fasth3_8step_v2_pruned_bf16 and int8_convrot), template video_fastvideo_fasth3_i2v.json. Ref2VA was not distilled. FastVideo's own CUDA example basic_fasth3_8step.py is still prompt-only.
• FastVideo main (read 2026-09-22) still documents the MLX entry as T2VA only. The Apple Silicon guide and the H3 cookbook both list FL2VA as not wired. generate() has no image latent, mask, or conditioning-row argument. vanch007/FastVideo-FastH3-8-Step-V2-MLX-INT8 calls that same text-only generate().
• Apple Silicon runtimes that do anchor a frame load a different DiT. appautomaton/mlx-h3 (appautomaton/minimax-h3-base-8bit-mlx, dit_fl2va_a8g32) and PortOS's existing minimax_h3 rows (PipeNetwork 4/6/8-bit) are the base FL2VA model. They do not carry V2's eight-rung ladder or VSA routing tensors, so they cannot satisfy this issue's schedule and cache-identity acceptance.

Decision: leave fasth3_v2_int6 / fasth3_v2_int8 text-only. Image and first/last-frame stays on the MiniMax H3 MLX rows. A PortOS-only mask adapter would reimplement the Comfy algorithm inside a pipeline that has no hook, and there is still no Apple Silicon render of the upstream path to compare against.

Reopen implementation when FastVideo's MLX entry accepts a first frame on FastVideo/FastVideo-FastH3-8-Step-V2 @ 3da2ddfe1954d9cda4c05b643dc0f26007a655c5 (or a successor sidecar with the same eight-rung ladder) while keeping shifts, VSA 0.8 / tile 64, the int6/int8 cache identity, and synchronized 24 fps audio.

Write-up: docs/research/2026-09-22-fasth3-v2-mlx-i2v.md.