Mask the NVIC bitmap index so the accessors need no bounds check.

[CordlessCoder]

NVIC's interrupt-bitmap accessors index a 16-word array with nr / 32:

unsafe { (*Self::PTR).ispr[usize::from(nr / 32)].write(1 << (nr % 32)) }

nr comes from InterruptNumber::number() -> u16, so the optimiser thinks nr / 32 is 0..2048 against an array of 16. Each accessor keeps a bounds check, a panicking branch, and a reference to panic_bounds_check.

Ten call sites across nine methods: mask, unmask, is_enabled, is_active, is_pending, pend, unpend, and the ARMv8-M route_to_nonsecure, route_to_secure and is_routed_to_nonsecure.
This replaces them with one private helper that masks the index to the array's own bound.

Why this isn't a breaking change

No Cortex-M profile implements more than 496 external interrupts, so nr / 32 is at most 15 on every architecture this crate supports and the mask never alters a legal index.

Measurement

embassy's examples/rp multiprio binary, rp2040, thumbv6m, release:

variant	.text
control	16340 B
this change	16120 B
delta	−220 B

[diondokter]

Looks good. Nice and straightforward now

[adamgreig]

Just to confirm, @CordlessCoder you still see the same binary size improvement and lack of panic path in the current version of the PR?

[CordlessCoder]

@adamgreig Yes, panic_bounds_check is still absent from the version with the PR and present without it. Same -220B flash difference.