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Add introductory Verilog lessons#8

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thomasnormal:mainfrom
samir-shah-ahmed:add-verilog-lessons
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Add introductory Verilog lessons#8
samir-shah-ahmed wants to merge 1 commit into
thomasnormal:mainfrom
samir-shah-ahmed:add-verilog-lessons

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@samir-shah-ahmed

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Closes #4

Adds 8 introductory Verilog lessons as a stepping stone before the SystemVerilog content:

  • intro
  • gates
  • wires-regs
  • operators
  • always-blocks
  • if-case
  • modules
  • testbench

Each lesson includes a description and starter/solution .sv files. I'm still learning so feedback on any mistakes is welcome!

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Adding Verilog to the start of the tutorial

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