Align data buffers in fastlanes benchmarks#8393
Conversation
Signed-off-by: Adam Gutglick <adam@spiraldb.com>
Merging this PR will degrade performance by 12.75%
|
| Mode | Benchmark | BASE |
HEAD |
Efficiency | |
|---|---|---|---|---|---|
| ❌ | Simulation | baseline_lt[16, 65536] |
219.3 µs | 304.8 µs | -28.04% |
| ❌ | Simulation | baseline_eq[4, 65536] |
186.9 µs | 244.4 µs | -23.53% |
| ❌ | Simulation | baseline_lt[4, 65536] |
202.6 µs | 259.6 µs | -21.97% |
| ❌ | Simulation | baseline_eq[16, 65536] |
231.8 µs | 289.4 µs | -19.89% |
| ❌ | Simulation | fast_lt_out_of_range[16, 65536] |
120.5 µs | 148.4 µs | -18.8% |
| ❌ | Simulation | compare[12] |
115.9 µs | 136.5 µs | -15.15% |
| ❌ | Simulation | varbinview_large |
112.9 µs | 131.5 µs | -14.14% |
| ❌ | Simulation | decompress_rd[f64, (100000, 0.01)] |
845.9 µs | 981.5 µs | -13.82% |
| ❌ | Simulation | decompress_rd[f64, (100000, 0.1)] |
845.9 µs | 981.5 µs | -13.82% |
| ❌ | Simulation | compare[8] |
105 µs | 118.3 µs | -11.25% |
| ❌ | Simulation | compare[10] |
135.9 µs | 152.9 µs | -11.1% |
| ⚡ | Simulation | decompress_rd[f64, (100000, 0.0)] |
1,024.6 µs | 845.8 µs | +21.14% |
| ⚡ | Simulation | decompress_rd[f32, (100000, 0.0)] |
586.8 µs | 499.3 µs | +17.53% |
Tip
Investigate this regression by commenting @codspeedbot fix this regression on this PR, or directly use the CodSpeed MCP with your agent.
Comparing adamg/align-buffers-benchmarks (3abc40b) with develop (37ae2d7)
Footnotes
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10 benchmarks were skipped, so the baseline results were used instead. If they were deleted from the codebase, click here and archive them to remove them from the performance reports. ↩
Summary
An experiment to align the packed buffers in the benchmarks to try and reduce some of the noise around the
comparebenchmark. If this works maybe its a path towards more consistent benchmarks?