JIT: contain shifts into byref ADD on arm64

[EgorBo]

Experiment to get the SPMI diffs. On arm64 IsContainableUnaryOrBinaryOp bails out for any byref-producing parent (TYP_BYREF has no VTF_INT), so shifts are never folded into ref-based address arithmetic:

;; base + (index * 24), e.g. CastCache.TryGet

-            add     w5, w3, #1
-            add     x5, x5, x5,  LSL #1
-            lsl     x5, x5, #3
-            add     x5, x5, x0
-            ldar    w6, [x5]
+            add     w5, w3, #1
+            add     x5, x5, x5,  LSL #1
+            add     x5, x0, x5,  LSL #3
+            ldar    w6, [x5]

Some noticeable diffs

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[Copilot]

Pull request overview

Enables ARM64 containment of shift/mul (and related) unary/binary ops under byref-producing parents so address arithmetic like base + (index << cns) can be emitted as a single add ... LSL #imm form instead of separate lsl + add.

Changes:

• Allow TYP_BYREF parents in Lowering::IsContainableUnaryOrBinaryOp on ARM64.
• Relax ARM64 codegen debug assertions for contained MUL/SHIFT/ROR/CAST cases to permit TYP_BYREF results.

Reviewed changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.

File	Description
src/coreclr/jit/lowerarmarch.cpp	Permits containment decisions for byref-typed parents so shifts/muls can fold into byref address arithmetic.
src/coreclr/jit/codegenarm64.cpp	Updates asserts to allow byref-typed binary results when emitting combined ops (e.g., add ... LSL #imm, madd).

[adamperlin]

Are there any particular downsides here? This seems like a minimal code change for some pretty positive diffs!

[EgorBo]

Are there any particular downsides here? This seems like a minimal code change for some pretty positive diffs!

Shouldn't be any, just didn't plan to merge it into .NET 11 🙂

[Copilot]

Pull request overview

Copilot reviewed 2 out of 2 changed files in this pull request and generated no new comments.

Suppressed comments (1)

src/coreclr/jit/lowerarmarch.cpp:200

• The comment describing the parent-node type restriction is now slightly inaccurate: TYP_BYREF parents are allowed (for address arithmetic), even though they're not integral. Updating the bullet helps future readers understand why the byref exception exists.

    if (parentNode->isContained())
        return false;

    if (!varTypeIsIntegral(parentNode) && !parentNode->TypeIs(TYP_BYREF))
        return false;

[adamperlin]

Are there any particular downsides here? This seems like a minimal code change for some pretty positive diffs!

Shouldn't be any, just didn't plan to merge it into .NET 11 🙂

Ah got it, for .NET 12 then! 🚀

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[Copilot]

Pull request overview

Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.

Suppressed comments (3)

src/coreclr/jit/lowerarmarch.cpp:200

• The comment above this check says the parent must be “operating on an integer”, but this change explicitly allows TYP_BYREF parents as well. Updating the comment avoids future confusion about why BYREF is permitted here.

    if (!varTypeIsIntegral(parentNode) && !parentNode->TypeIs(TYP_BYREF))
        return false;

src/coreclr/jit/codegenarm64.cpp:2802

• This path can now produce BYREF results (due to the updated asserts). The emitAttr passed to emitIns_R_R_R_I should include EA_BYREF_FLG when tree is TYP_BYREF; otherwise the emitter will treat the destination as non-byref for GC/byref liveness updates.

        // ROR is only contained under AND/OR/XOR parents, which are never TYP_BYREF.

src/coreclr/jit/codegenarm64.cpp:2845

• Similar to the MUL/shift contained paths, this contained CAST path can now produce a TYP_BYREF result. The emitIns_R_R_R call uses emitActualTypeSize(tree) (size-only), so it won’t mark the instruction as producing a byref in the emitter’s idGCref tracking. The emitted instruction should use an emitAttr with EA_BYREF_FLG when tree->TypeIs(TYP_BYREF).

        assert(varTypeIsIntegral(tree) || tree->TypeIs(TYP_BYREF));